Flip-flop circuit

ABSTRACT

A flip-flop circuit includes a first inverter including a first insulated gate field-effect transistor (MISFET), a second MISFET for storage, and a third MISFET for control of writing and a fourth MISFET, the second and third MISFET&#39;&#39;s being connected in series between the first and fourth MISFET&#39;&#39;s. A fifth MISFET for receiving an input signal and a sixth MISFET for control of writing are connected between the first and fourth MISFET&#39;&#39;s. A second inverter including a seventh MISFET for storage and a MISFET for a load thereof are connected in series with each other, an output terminal of the second inverter being feedbackconnected to an input electrode of the second MISFET. An eighth MISFET for transfer is connected between an output terminal of the first inverter and an input electrode of the seventh MISFET. The third MISFET is rendered non-conductive and the sixth MISFET conductive at writing when at least the fourth and eighth MISFET&#39;&#39;s are conductive.

Hittite Hatsukano et al.

States Patent 1 FLIP-FLOP CIRCUIT [751 Inventors: Yoshikazu Hatsukano;Kosei Nomiya; Shuichi Torii, all of Tokyo,

Japan [73] Assignee: Hitachi, Ltd., Tokyo, Japan [22] Filed: June 26,1973 [21] Appl. N0.: 373,761

[30] Foreign Application Priority Data 45] May 28, 1974 PrimaryExaminer-John S. Heyman Attorney, Agent, orFirm-Craig and Antonelli [57]ABSTRACT A flip-flop circuit includes a first inverter including a firstinsulated gate field-effect transistor (MISFET). a second MISFET forstorage, and a third MlSFET for control of writing and a fourth MISFET,the second and third MISFETs being connected in series between the firstand fourth MlSFETs. A fifth MlSFET for receiving an input signal and asixth MISFET for control of writing are connected between the first andfourth MlSFETs. A second inverter including a seventh MIS- FET forstorage and a MlSFET for a load thereof are connected in series witheach other, an output terminal of the second inverter beingfeedback-connected to an input electrode of the second MlSFET. An eighthMlSFET for transfer is connected between an output terminal of the firstinverter and an input electrode of the seventh MISFET. The third MlSFETis rendered non-conductive and the sixth MlSFET conductive at writingwhen at least the fourth and eighth MlSFETs are conductive.

6 Claims GDrawing Figures PATENTEDMAYZBIHM I 3.813.564

sum 1-1! 2 PRIOR ART FIG. 2

PRIOR ART Vss Vow n; FL ['1 1 FLIP-FLOP CIRCUIT BACKGROUND OF THEINVENTION 1. Field of the Invention The present invention relates to aflip-flop circuit and more particularly to a static flip-flop circuitcomposed of insulated gate field-effect transistors.

2. Description of the Prior Art I Flip-flop circuits composed ofinsulated gate fieldeffect transistors (hereinafter simply termedtransistors) are broadly classified as dynamic flip-flop circuits andstatic flip-flop circuits. Since the dynamic flip-flop circuit is simplein construction, it is often employed in devices such as shift registersin which a number of flipflop circuits are connected in cascade. In thecase where the period for Writing information into the flipflop circuitis long, the static flip-flopcircuit having a feedback path is moresuitable.

Examples of typical static flip-flop circuits are shown in FIGS. 1 and2. The static flip-flop circuit in FIG. 1 is constructed of a firstinverter circuit composed of transistors Q21 and Q22, 21 second invertercircuit composed of transistors Q23 and Q24, a third inverter circuitcomposed of transistors Q25 and Q26, and transistors O which serve astransfer gates. The second inverter circuit and the third invertercircuit are connected in cascade. The output terminal of the thirdinverter circuit is feedback-connected through the transfer gatetransistor 0 to the input terminal of the second inverter circuit, andinformation is statically retained by the feedback loop. The contents ofthe information to be retained by the feedback loop are determined by aninput signal V,-,,, when the transfer gate transistor Q2 is turned on bya writing control clock pulse (b The gate electrodes of the transistorsQ23 and Q29 are connected to receive clock pulses qb shown in FIG. 3b,while the gate electrode of the transistor 0 receives the writingcontrolclock pulses (p which differ in phase from the pulses The respectivedrain electrodes of the load transistors O21, Q23 and 0 are connected toreceive a negative DC voltage V,,,',, and the respective gate electrodesare connected to a negative DC voltage V which is larger than thevoltage V by the threshold voltage V of the transistors, i.e., more thanuci l nu|+l mi)- On account of the well-known substrate effect, thevoltage to be applied to the gate electrodes of the transfer gatetransistors Q Q requires as high a level as the load transistors Q2, Q2and Q25 (for example, the same level as that of the voltage V Thesubstrate effect arises for the reason that, in the case where thesubstrates of the respective transistors are commonly connected to areference potential point (for example, in an integrated semiconductorcircuit, the respective transistors have a single common semiconductorsub strate), a voltage is impressed between the source electrode of eachtransistor and the substrate. The clock pulses Q5 and are thereforegenerated at high voltage level outside the integrated semiconductorcircuit device.

On the other hand, the writing control clock pulse is generated bytaking, as shown in FIG. 3a, the logic result between the clock pulsed), and a control signal X generated in, for example, an electroniccomputer. The logic result is established by a logic circuit consistingof transistors 031 Q:::;, the logic circuit being 2 similarlyincorporated within the integrated semiconductor circuit in which theflip-flop circuit is constructed. Herein, the output potential of thelogic circuit'falls to an electric potential approximately equal tothevoltage V In general, accordingly, in order to raise the outputpotential, level conversion is performed by a circuit outside theintegrated semiconductor circuit device to convert the output pulse to aclock control pulse of high level. It is also thought that, with anidentical integrated semiconductor circuit device, the output level ofthe logic circuit can be raised by additionally providing one powersource. However. it is inevitable that the number of external terminalsof the integratedcircuit device must be increased with such anarrangement, and therefore the specification of the integrated circuitdevice is subject to restriction.

When, in the'static flip-flop circuit of FIG. 1, the load transistors021 023 and 0 5 are provided for clock drive in order to reduce powerconsumption, so-called charge sharing arises. It is accordingly fearedthat an erroneous operation will occur.

On the other hand, with the static flip-flop circuit of FIG. 2, sincethe source electrodes of the transistors Q1 and Q -for control ofwriting are grounded,- the aforesaid substrate effect does not occur,and the voltage level of the writing control pulse (15,, may be low.Since the output terminal of an inverter circuit composed of transistorsO2 and Q, is directly feedback-connected to the input terminal of aninverter circuit composed of transistors Q and O without theintervention of the transfer gate Q of FIG. 1, the aforesaid chargesharing problem does not result, and'the load transistors Q1 and O canbe clock-driven. As will now be explained, however, another problemarises with the circuit of FIG. 2.

The clock control pulse (15 is formed by the logic circuit consisting ofthe transistors Q 1 Q which receives the clock pulse and the controlsignal X as its input signals, as shown in FIG. 3a. In consequence, theclock control pulsed) lags over the clock pulse d), as shown in FIG. 3b.Accordingly, the period oftime during which the .clock pulsed), and theclock control pulse overlap, in other words, the period of time duringwhich transistors Q and Q and transistors Q3 and O are simultaneouslyrendered conductive for the writing operation,is made shorter than thepulse width of the clock pulse (I) by the delay of the logic circuit, asillustrated by the hatched portion seen in FIG. 3b. The fact that thetime interval of the concurrent conduction of the transistors is short,leads to the result that the period of time for writing the input signalV, into the flip-flop circuit is short. Unfortunately, this may cause anerroneous operation. For example, if the time interval of simultaneousconduction of the transistors Q and O is short, the possibility oferroneous operation due to the relationship between the discharge timeconstant of a circuit made up of the transistors Q Q Q and Q, a voltageretained in the gate capacity of the transistor 0., and the thresholdvoltage V of the transistor 0., may result. If the simultaneousconduction time of the transistors Q and O is short, the possibility ofan erroneous operation due to the relationship between the charge timeconstant of a circuit consisting of the transistors Q1, Q and Q4, thesupply voltage V and the threshold voltage V of the transistor 0 mayoccur. The latter case produces an especially difficult problem duringcharging. In order to prolong the overlapping period of time between theclock pulse (1), and the clock control pulse (1) the pulse width of theclock pulse 4), may be made suffrciently long. To this end, however, itis necessary to lower the clock frequency, which makes it inevitablethat the speed of the shift register or the like must be lowered.

SUMMARY OF THE INVENTION the occupying area of which within anintegrated semiconductor circuit is made small.

The other objects of the present invention will be apparent from thefollowing detailed description when read in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are schematic circuitdiagrams of the prior art static flip-flop circuit previously expalined,

FIG. 3a is a schematic diagram of the logic circuit referred to in theprevious description for producing the writing control signal (in, ofthe clock pulse :1), and the control signal X;

FIG. 3!; illustrates the clock pulses 5, and (1) the control signal Xandthe writing control clock pulse 1 11;

FIG. 4 is a schematic circuit diagram showing an embodiment of aflip-flop circuit according to the present invention; and

FIG. 5 is a waveform diagram for explaining the circuit of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 4 shows an embodiment ofthe static flip-flop circuit according to the present invention. In thefigure, the same parts as, or parts having the same function as, thecircuit of FIG. 2 are identified by common symbols. The elements O11, Qand Q20 in FIG. 4 are MOS fieldeffect transistors. A capacitor C,corresponds to the junction capacities of the transistors Q Q and Q andthe capacities ofconnections for coupling these transistors to thetransistor A capacitor C corresponds to the gate capacity of thetransistor 04 and the connection capacity between the transistors Q andQ The capacity of the capacitor C is set at a value larger than thecapacity of the capacitor C As the capacitor C,, a separate capacitormay be employed, connected between the drain electrode of the transistorQ ground.

The drain electrode of the transistor Q is connected to the sourceelectrode of the transistor Q and the gate electrode is connected toreceive a signal X, which corresponds to an inverted writing controlsignal X, by way of an inverter IN. The drain electrode of thetransistor Q is commonly connected to the source electrodes of thetransistors Q1 and 0 while the source electrode is grounded. In thiscase, the gate electrode of the transistor 0 is connected to receive theclock and i pulse 4),. Further, unlike the gate electrode of thetransistor Q, in FIG. 2, the gate electrode of the transistor Q issupplied with the clock pulse The writing control signal X applied tothe gate electrode of the transistor O is adapted to bring thetransistor 0, into the on state and the transistor Q into the of state.while at least the transistors Q andd Q are in the on" state duringwriting of information.

The operation of the static flip-flop circuit according to the presentinvention'will now be explained with reference to the waveform diagramof FIG. 5. In the figme, the upper level of each signal indicates thelogic 1 (ground potential), while the lower level indicates the logic 0(negative potential). The writing control signal X employed herein isone which, similarly to the input signal V,-,,, is synchronized with theclock pulses (1) and has a pulse width equal to the period of the clockpulses 1. Before the clock pulse (35, becomes 0 to render thetransistors Q and Q conductive, the capacitor C is previously chargedduring the 0 period of the clock pulse In the waveform diagramof FIG. 5,the capacitor C, is charged between times t and t 2. When the writingcontrol signal X becomes 0, the transistor O1 becomes conductive and thetransistor 0 becomes non-conductive. When the clock pulse 4), falls to 0in this period, whether or not the charges stored in the capacitor C, orC are discharged through the transistors Q3, Q6: Q1 and Q2 is determinedirrespective of the previous old information which has been stored inthe transistor Q (since the transistor Q is nonconductive) and independence on new information V,-,,. The result is stored in thecapacitor C Referring to FIG. 5, since the writing control signal X is 0during the period t, t thetransistor O is conductive and the transistorQ non-conductive during the period. Since the transistors Q and Q areconductive during the period t the charges accumulated in the capacitorC or C are determined by the discharge irrespective of the previousinformation stored in the transistor Q and in dependence on whether thetransistor O is rendered conductive or not (that is, by the input signalV I Assuming that the input signal V is l'during this period, as isillustrated in FIG. 5, the charges which have been previouslyaccumulated in the capacitor C or the charges which have beenaccumulated in the capacitor C before the time t,, are not discharged.Accordingly, either case occurs where the charges are left in thecapacitor C as they are or where charges are supplied thereto anew fromthe capacitor C,. In either case, charges are present in the capacitor CAs illustrated in FIG. 5, the writing operation is similarly performedinia period from time t to time t During the period, however, the inputsignal V,-,, is 0, so that the charges which have been accumulated inthe capacitors C and C are discharged through the transistors Q Q Q andQ In this way, the writing of the input signal V, into the flip-flopcircuit is completed.

3. On the other hand, when the writing control signal X becomes 1, thetransistor 0 becomes nonconductive, and the transistor Q18 becomesconductive. When the clock pulse (1), falls to 0 in the period, thecharges accumulated in the capacitor C or C are determined as to whetherthay are dischargedthrough the transistors Q3 O5, 018 and Q2 or not,independently of the input signal V (since the transistor O isnonconductive) and by the previous old information stored in thetransistor Q The result is stored in the capacitor C again;

Referring to FIG. 5, since the writing control signal X is 1 during aperiod from time to time 1 the transistor O is non-conductive and thetransistor O conductive during the period. Since the transistors Q3 andQ are conductive during a period t, t the charges accumulated in thecapacitor C, or C are determined as to the discharge irrespective of theinput signal V,-, and in dependence on whether the transistor O isrendered conductive or not, that is, by the previous old informationaccumulated in the gate capacity of the transistor Q The information tobe stored in the transistor O is determined by the information stored inthe'capacitor C It will be 1 if the information stored in the capacitorC is 0, and it will be if the same is 1. Therefore, since theinformation 0 has been perfectly stored in the capacitor C at the time tas in explanation (2) above, the information I is stored in thetransistor 0 and the charges which have been accumulated in thecapacitors C and C are not discharged. In consequence, the charges areleft in the capacitor C as they are, and some charges having leakedtherefrom in a period 1 t, are again supplied thereto from the capacitorC,. In other'words, while the writing control signal X is l, theinformation once stored in the transistors Q, and 0 are retained as theyare.

4. During a period during which the clock pulse (11 is of 0, an invertedsignal corresponding to the information stored in the capacitor C isderived as the output signal V from the transistor Q For example,negative charges are accumulated in the capacitor C during a period t sothat the transistor 0 is conductive and the outputsignal V is at groundpotential (logic 1). Similarly, the transitor Q, is non-conductiveduring a period 1 t,,, so that theoutput signal V0111 is 0. In thismanner, the reading operation is carried out.

The static flip-flop circuit according to the present invention as hasthus far been described, has the following merits:

1. Since the pulse width of the clock pulse (1), can be exploited by 100percent, the frequency of the clock pulses can be raised. 7

When the writing control signal X, as shown in FIG. 3b or FIG. 5, isused as the writing control pulses in the static flip-flop circuit ofFIG. 2, the following erroneous operation arises. In the case where thewriting control signal is 0, the transistor 0,, is always renderedconductive during the reading operation (when the clock pulse b becomes0), and the output signal V is always brought to ground potentialindependently of the input signal V,-,,. More specifically, in order todisconnect the feedback loop and offer a preference to the input signalin case of writing a new information, the transistor O8 is renderedconductive to make the gate voltage of the transistor 0,, zero volt. Theprior-art circuit therefore cannot employ such writing control signal X.

In contrast, with the static flip-flop circuit according to the presentinvention, as shown in FIG. 4, the transistor O is renderednon-conductive in order to disconnect the feedback loop and givepriority to the input signal V in the case of writing a new information.Therefore, the gate voltage of the transistor 0, or the output signalV,,,,, is not influenced by the control signal X at all, and theaforesaid object of the present invention is accomplished. The writingcontrol signal X may become 0 during the writing operation when at leastthe c lock pulse (1), becomes 0. The writing control signal X need be asignal which becomes 1 at least at that time in order to make unrelatedthe previous information accumulated in the transistor 0 2. As comparedwith the circuit in FIG. 2, the embodiment in FIG. 4 is larger by thetwo additional -transistors employed. With the circuit of the presentinvention, however, the transistor O for charging the capacitor C, andthe series circuit member of the transistors Q Q and Q as well as theseries circuit member of the transistors Q5, Q and 0 the series circuitmembers forming under the specified conditions the conduction paths fordischarging charges accumulated in the capacitor C separately effect thecharging and discharging operations for the capacitor C by the use ofthe clock pulses (I), and 4);, which differ in phase. Hence, thenecessity for considering the resistance ratio between both theconstituents as in the prior art is eliminated. It is accordinglyunnecessary to form the transistors 0 Q6, 01,0 and Q at larger areasrelative to the transistor Q in the integrated semiconductor circuit. Insubstance, the circuit ofthe invention can be formed in an area smallerthan that of the circuit in FIG. 2.

3. The source electrodes of the transistors 01 and 018 are essentiallyequivalent to being grounded. Consequently, the substrate effect doesnot become a problem, which makes it possible to use a writing controlsignal of low level.

Although, in the embodiment, the transistor O is employed as the load ofthe transistor Q4, it may be replaced with a usual impedance element oran element having a similar performance so as to drive the transistor Q,with a DC voltage. Although, in the embodiment, the input signal V issupplied to the transistor Q,,-,it may of course be made to feed theinput signal V to the transistor Q and to apply the writing controlsignal X to the transistor Q Although, in the embodiment, the MOSfield-effect type transistor is employed, it is a matter of course thatthey are not restricted thereto insofar as the MIS field-effect type maybe utilized.

As stated above, in accordance with the flip-flop circuit of thepresentinvention, such various advantageous results are produced thatthe pulse width of the clock pulse (by can be effectively exploited by100 percent and that the occupying area of the flip-flop circuit in anintegrated circuit can be made small.

What is claimed is:

l. A flip-flop circuit comprising a voltage source, a first invertercircuit .including a first impedance element and first and secondinsulated gate field-effect transistors connected in series across saidvoltage source, third and fourth insulated gate field-effect transistorsconnected in series across said first insulated gate field-effecttransistor, a second inverter circuit inlated gate field effecttransistors, and Output means for deriving an output signal from theinput electrode of said fifth insulated gate field-effect transistor,the output terminal of said second inverter circuit being feedbackconnected to the input electrode of said first insulated gatefield-effect transistor.

2. A flip-flop circuit as defined in claim 1 wherein said first andsecond impedance elements consist of eighth and ninth insulated gatefield-effect transistors.

3. A flip-flop circuit as defined in claim 2 further including gatingmeans for applying first gating signals to the input electrode of saidsecond insulated gate fieldeffect transistor and second gating signalsto the input electrodes of said eighth and ninth insulated gate fieldeffect transistors.

4. A flip-flop circuit as defined in claim 3 wherein said gating meansis connected to the input electrode of said sixth insulated gatefield-effect transistor to apply first gating signals thereto.

5. A flip-flop circuit as defined in claim 4 wherein said output meansincludes a tenth insulated gate fieldeffect transistor connected betweenthe point of connection of said fifth and ninth insulated gatefield-effect transistors and an output terminal.

6. A flip-flop circuit as defined in claim 5 wherein the input electrodeof said tenth insulated gate field-effect transistor is connected tosaid gating means to receive said second gating signals.

1. A flip-flop circuit comprising a voltage source, a first invertercircuit including a first impedance element and first and secondinsulated gate field-effect transistors connected in series across saidvoltage source, third and fourth insulated gate field-effect transistorsconnected in series across said first insulated gate field-effecttransistor, a second inverter circuit including a second impedanceelement in series with a fifth insulated gate field-effect transistoracross said voltage source, a sixth insulated gate field-effecttransistor connected between an output terminal of said first invertercircuit and the input electrode of said fifth insulated gatefield-effect transistor, a seventh insulated gate field-effecttransistor connected in series between said first and second insulatedgate field-effect transistors and having its input electrode connectedto the input electrode of one of said third and fourth insulated gatefield effect transistors, and output means for deriving an output signalfrom the input electrode of said fifth insulated gate field-effecttransistor, the output terminal of said second inverter circuit beingfeedback connected to the input electrode of said first insulated gatefield-effect transistor.
 2. A flip-flop circuit as defined in claim 1wherein said first and second impedance elements consist of eighth andninth insulated gate field-effect transistors.
 3. A flip-flop circuit asdefined in claim 2 further including gating means for applying firstgating signals to the input electrode of said second insulated gatefield-effect transistor and second gating signals to the inputelectrodes of said eighth and ninth insulated gate field effecttransistors.
 4. A flip-flop circuit as defined in claim 3 wherein saidgating means is connected to the input electrode of said sixth insulatedgate field-effect transistor to apply first gating signals thereto.
 5. Aflip-flop circuit as defined in claim 4 wherein said output meansincludes a tenth insulated gate field-effect transistor connectedbetween the point of connection of said fifth and ninth insulated gatefield-effect transistors and an output terminal.
 6. A flip-flop circuitas defined in claim 5 wherein the input electrode of said tenthinsulated gate field-effect transistor is connected to said gating meansto receive said second gating signals.